Pni ASIC Manuel d'utilisateur télécharger pdf (Page 10)

PNIASIC

HostProcessorInterface

Figure 5: SPI Port Full Timing Sequence (cpol = 0 )

Figure 6: SPI Port Timing Parameters (cpol = 0)

SPI Port Usage Tips

A SPI port can be implemented using different clock polarity options. The clock polarity used with the PNI ASIC

must be normally low, (cpol = 0).

Figure 6 graphically shows the timing sequence (cpol = 0). Data is always

considered valid while the SCLK is high (t

DASH

= Time, Data After SCLK High). When SCLK is low, the data is in

transition (t

DBSH

= Time, Data Before SCLK High).

When implementing a SPI port, whether it is a dedicated hardware peripheral port, or a software implemented port

using general purpose I/O (also known as Bit-Banging) the timing parameters given in

Figure 6 must be met to

ensure reliable communications. The clock set-up and hold times, t

DBSH

and t

DASH

must be greater than 100 nS.

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Pni ASIC Manuel d'utilisateur Page 10